TSMC began exploring panel level packaging, but Samsung started earlier?

Panel level packaging FO-PLP, a shortcut to doubling the production capacity of AI chips?

In fanout packaging, which accounts for 10% of the advanced packaging market, the main technical routes are divided into FOPLP (fanout panel level packaging) and FOWLP (fanout wafer level packaging). Compared to FOWLP, FOPLP can use cheaper and larger square substrates to package as many packages as possible on one substrate, thereby reducing packaging costs.
The size is exactly one of the major advantages of FOPLP. Compared to FOWLP using traditional 300mm wafers, the edge part cannot be utilized, and its area utilization rate is not high. On the other hand, FOPLP using square panels has a larger overall panel area and an area utilization rate of over 95%. According to Nikkei's disclosure, TSMC is currently testing rectangular substrates with dimensions of 510mm x 515mm, which have a usable area more than four times that of circular wafers.
But there are also significant challenges for FOPLP to invest in advanced packaging of various high-performance chips. Firstly, the size of FOWLP packaging has been standardized, and the relevant equipment and materials have matured. On the other hand, FOPLP still faces the problem of uneven substrate materials and size types.
wKgaomZ9PL2AN1uvAAO_rt8BzcU240.png
Another issue is line width. It is difficult for FOPLP to achieve the level of FOWLP in line width, and it is even more difficult to compete with silicon intermediate layers. Therefore, for high-performance chip designs that require higher integration, the current FOPLP solutions on the market are still difficult to meet the demand.

In terms of panel level packaging, TSMC has already taken a step slower

In fact, when it comes to the public research of wafer fabs on FO-PLP, Samsung did start researching earlier. Since 2015, Samsung has been promoting the joint development of FO-PLP by its subsidiary Samsung Electric and Samsung Electronics, and subsequently acquired the entire business, after experiencing a defeat with TSMC in the Apple smartphone processor market.
Google's Pixel 7 series integrates its self-developed Tensor G2 chip, manufactured based on Samsung's 5nm process node, and packaging is the first to use FO-PLP technology in mobile SoC. From this, it can be seen that Samsung has the mass production capability of FO-PLP packaging since 2023.
Not only Samsung, but also many packaging manufacturers have invested in FOPLP production lines, such as South Korean packaging factory Nepes, which has long started laying out FOPLP. Nepes provides a 600mmx600mm square panel solution, which increases the utilization efficiency by 5 times compared to a 300mm wafer area. Nepes completed customer validation in the third quarter of 2021 and began full mass production of FOPLP in the fourth quarter, while doubling production capacity in 2022 under strong market demand.
There are also panel manufacturers that are equally focused on FO-PLP, such as Qunchuang Optoelectronics. In order to activate the old production line of the panel factory, Qunchuang Optoelectronics has chosen to enter the local semiconductor packaging industry since 2019, converting the production line of the 3.5th generation panel into a high-value FOPLP semiconductor packaging production line. According to Qunchuang Optoelectronics, their semiconductor packaging developed on G3.5 FOPLP glass substrate has a size of 620mm x 750mm, which is 7 times the size of a 12 inch glass wafer. It also solves the problem of warping, has high energy efficiency, and can accommodate more I/O.
In addition to the aforementioned manufacturers, there are also many domestic and foreign manufacturers developing this packaging technology, such as Futianfeng Microelectronics (established by Tianma Microelectronics and Tongfu Microelectronics) and Yicheng Technology (incubated by Yisiwei Investment) in China, and Manz AG and Amkor in foreign countries.
Write at the end
Although FO-PLP appears to have many advantages, it remains to be verified whether it can be widely used in state-of-the-art HPC/AI chips. FO-PLP does not require state-of-the-art processes and equipment, so it was previously mainly used for PMIC, RF, and high-power, high current power semiconductors. If the issues of material and size standards are solved, and technical specifications such as line width can be guaranteed, while achieving lower costs and higher production capacity, FO-PLP is likely to become another strong technological route in the advanced packaging market.